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LT4256-3IGN Datasheet(PDF) 17 Page - Linear Technology |
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LT4256-3IGN Datasheet(HTML) 17 Page - Linear Technology |
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17 / 20 page ![]() LT4256-3 17 42563f APPLICATIO S I FOR ATIO Figure 16. High dV/dt MOSFET Turn-On Protection Circuit 4256 F16 R5 0.033 Ω LT4256-3 SENSE 13 10 12 5 7 8 16 15 1 2 4 9 VCC GATE VOUT FB PWRGD RETRY UV OV TIMER GND VCC 48V (SHORT PIN) Q1 IRF530 D1 CMPZ5241BS 11V D3 1N4148W R3 4.02k R2 4.02k R1 64.9k R7 100 Ω R9 4.02k R6 10 Ω R8 36.5k VOUT 48V 1.2A R4 27k CL C2 33nF C3 0.1 µF C1 10nF OPEN UV = 36V OV = 73V PWRGD = 40V GND D2 SMAT70A + Figure 17. Enhanced Output Pull-Down Circuit In order to use this feature as designed, a bidirectional Zener diode is needed for D1. When the LT4256-3 com- mands the MOSFET off (and a bidirectional Zener is used), the output discharges very slowly (tOFF = (CLOAD • VOUT)/ 130 µA). Several variations can be implemented to dis- charge the output faster. The recommeded method is shown in Figure 17 and uses an external PNP transistor, diode and resistor to discharge the output quickly. 4256 F17 R5 0.010 Ω LT4256-3 SENSE 13 RPROG Q2 2N4920 D3 1N4148 RB 18k 10 5 7 8 16 15 1 2 4 9 VCC GATE FB 12 VOUT PWRGD RETRY UV OV TIMER GND VCC 48V (SHORT PIN) Q1 IRF540 D1 CMPZ5241BS 11V R3 4.02k R2 4.02k R1 64.9k R7 100 Ω R9 4.02k R6 1k R8 36.5k VOUT 48V 4A R4 51k CL C2 33nF C3 0.01 µF C1 10nF OPEN UV = 36V OV = 73V PWRGD = 40V GND D2 SMAT70A + The equation to set the nominal discharge current is: I R A DISCHG PROG =µ () 5000 130 (11) where RPROG must be less than 1k. The maximum current equation is: I R A MAX PROG =µ () 7000 350 (12) |
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