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LT4256-3

42563f

This open FET condition can be falsely signalled during

start-up if the load is not activated until after PWRGD goes

high. To avoid this false indication, OPEN and PWRGD

should not be polled for a period of time, tSTARTUP, given

by:

STARTUP

••

(9)

This can be accomplished either by a microcontroller (if

available) or by placing an RC filter as shown in Figure 13.

Once the OPEN voltage exceeds the monitoring logic thresh-

old, VTHRESH, and PWRGD is low, an open FET condition

is signalled. In order to prevent a false indication, the RC

product should be set with the following equation:

LOGIC

THRESH

















••

–

(10)

Another condition that can cause a false indication is if the

LT4256-3 goes into current limit during start-up. This will

cause tSTARTUP to be longer than calculated. Also, if the

LT4256-3 stays in current limit long enough for TIMER to

fully charge up to its threshold, the LT4256-3 will either

latch off (RETRY = 0) or go into the current limit hiccup

mode (RETRY = floating). In either case, an open FET

condition will be falsely signalled. If the LT4256-3 does go

into current limit during start-up, C1 can be increased (see

Power-Up Sequence).

APPLICATIO S I FOR ATIO

Supply Transient Protection

The LT4256-3 is 100% tested and guaranteed to be safe

from damage with supply voltages up to 80V. However,

voltage transients above 100V may cause permanent

damage. During a short-circuit condition, the large change

in currents flowing through the power supply traces can

cause inductive voltage transients which could exceed

100V. To minimize the voltage transients, the power trace

parasitic inductance should be minimized by using wider

traces or heavier trace plating and a bypass capacitor

should be placed between VCC and GND. A surge suppres-

sor (TransZorb

®) at the input can also prevent damage

from voltage transients.

GATE Pin

A curve of gate drive vs VCC is shown in Figure 14. GATE

is clamped to a maximum voltage of 12.8V above VOUT.

This clamp is designed to withstand the internal charge

pump current. An external Zener diode must be used as

shown in all applications. At a minimum input supply

voltage of 10.8V, the minimum gate drive voltage is 4.5V.

When the input supply voltage is higher than 20V, the gate

drive voltage is at least 10V and a standard threshold

MOSFET can be used. In applications from 12V to 15V

range, a logic level MOSFET must be used.

Figure 13. Delay Circuit for OPEN FET Detection

4256 F13

OPEN

LT4256-3

MONITORING

LOGIC

VLOGIC

INTERNAL

OPEN COLLECTOR

PULL-DOWN

Figure 14.

∆VGATE vs VCC

VCC (V)

4256 F14

TransZorb is a registered trademark of General Instruments, GSI.

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