PR601

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Product data sheet

COMPANY PUBLIC

Rev. 3.3 — 10 March 2016

219333

2 of 14

NXP Semiconductors

PR601

High performance NFC integrated reader solution

demodulation and decoding signals from ISO 14443A/MIFARE compatible cards and

transponders. The digital module manages the complete ISO 14443A framing and error

detection (parity and CRC) functionality. The CLRC663 supports MIFARE 1K, MIFARE

4K, MIFARE Ultralight, MIFARE, Ultralight C, MIFARE PLUS and MIFARE DESFire

products. The CLRC663 supports contactless communication and uses MIFARE higher

transfer speeds up to 848 kBd in both directions.

The CLRC663 supports all layers of the ISO/IEC 14443B reader/writer communication

scheme, given correct implementation of additional components, like oscillator, power

supply, coil etc. and provided that standardized protocols, for example, like ISO/IEC

14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented.

Enabled in Reader/Writer mode for FeliCa, the CLRC663 transceiver IC supports the

FeliCa communication scheme. The receiver part provides a robust and efficient

implementation of the demodulation and decoding circuitry for FeliCa coded signals. The

digital part handles the FeliCa framing and error detection like CRC. The CLRC663

supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s

in both directions. The CLRC663 supports vicinity protocol according to ISO/IEC15693,

EPC UID and ISO/IEC 18000-3 mode 3. The complete vicinity product family of NXP is

supported and enable a readability for mid-ranger reader applications.

The following host interfaces are provided:

2.2 LPC1227

The LPC1227 are ARM Cortex-M0-based microcontrollers for embedded applications

featuring a high level of integration and low-power consumption. The ARM Cortex-M0 is a

next generation core that offers system enhancements such as enhanced debug features

and a higher level of support block integration. In addition to the ARM Cortex-M0, the

LPC1X features an event handler API to limit the interrupt load of the ARM Cortex-M0

CPU and to allow for additional power-savings by off-loading event handling from the

main CPU.

The LPC1227 operates at CPU frequencies of up to 33 MHz and include up to 128 kB of

flash memory and 8 kB of data memory.

Not all connections of the LPC1227 product are implemented by the PR601.

3.

Features and benefits