6
Proprietary to OmniVision Technologies
Version 1.4, March 6, 2003
OV7640/OV7141
CMOS VGA (640 x 480) CAMERACHIP™
Omni ision
Table 4
Functional and AC Characteristics (0°C < TA < 70°C)
Symbol
Parameter
Min
Typ
Max
Unit
Functional Characteristics
A/D
Differential Non-Linearity
+ 1/2
LSB
A/D
Integral Non-Linearity
+ 1LSB
AGC
Range
21
dB
Red/Blue Adjustment Range
12
dB
Inputs (PWDN, CLK, RESET)
fCLK
Input Clock Frequency
10
24
27
MHz
tCLK
Input Clock Period
100
42
37
ns
tCLK:DC
Clock Duty Cycle
45
50
55
%
tS:RESET
Setting time after software/hardware reset
1
ms
tS:REG
Settling time for register change (10 frames required)
300
ms
SCCB (SIO_C and SIO_D - see Figure 4)
fSIO_C
Clock Frequency
400
KHz
tLOW
Clock Low Period
1.3
μs
tHIGH
Clock High Period
600
ns
tAA
SIO_C low to Data Out valid
100
900
ns
tBUF
Bus free time before new START
1.3
μs
tHD:STA
START condition Hold time
600
ns
tSU:STA
START condition Setup time
600
ns
tHD:DAT
Data-in Hold time
0
μs
tSU:DAT
Data-in Setup time
100
ns
tSU:STO
STOP condition Setup time
600
ns
tR, tF
SCCB Rise/Fall times
300
ns
tDH
Data-out Hold time
50
ns
Outputs (VSYNC, HREF, PCLK, and Y[7:0] - see Figure 5, Figure 6, and Figure 7)
tPDV
PCLK[ ] to Data-out Valid
5
ns
tSU
Y[7:0] Setup time
15
ns
tHD
Y[7:0] Hold time
8
ns
tPHH
PCLK[ ] to HREF[ ]0
5
ns
tPHL
PCLK[ ] to HREF[ ]0
5
ns
AC
Conditions:
VDD:
VDD-A = VDD-C = 2.5V, VDD-IO = 3.3V
Rise/Fall Times: I/O:
5ns, Maximum
SCCB: 300ns, Maximum
Input Capacitance: 10pf
Output Loading: 25pF, 1.2K
to 3V
fCLK:
24MHz
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