845GE datasheet(21/176 Pages) INTEL

21 / 176 page

Intel® 82845GE/82845PE Datasheet

Signal Description

This section provides a detailed description of (G)MCH signals. The signals are arranged in

functional groups according to their associated interface.

The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when

the signal is at a low voltage level. When “#” is not present after the signal name the signal is

asserted when at the high voltage level.

The following notations are used to describe the signal type:

Input pin

Output pin

I/O

Bi-Directional Input/Output pin

s/t/s

Sustained Tri-State. This pin is driven to its inactive state prior to tri-stating.

The signal description also includes the type of buffer used for the particular signal:

AGTL+

Open Drain AGTL+ interface signal. The (G)MCH integrates AGTL+

termination resistors, and supports VTT from 1.15 V to 1.75 V

AGP

AGP interface signals. These signals are compatible with the Accelerated

Graphics Port Interface Specification, Revision 2.0 1.5 V Signaling Environment

DC and AC Specifications. The buffers are not 3.3 V tolerant.

LVTTL

Low Voltage TTL 3.3 V compatible signals

SSTL_2

Stub Series Terminated Logic 2.5 V compatible signals.

CMOS

CMOS buffers.

Host Interface signals that perform multiple transfers per clock cycle may be marked as either

“4X” (for signals that are “quad-pumped”) or 2X (for signals that are “double-pumped”).

Note that processor address and data bus signals are logically inverted signals. In other words, the

actual values are inverted of what appears on the processor bus. This must be taken into account

and the addresses and data bus signals must be inverted inside the (G)MCH host bridge. All

processor control signals follow normal convention. A 0 indicates an active level (low voltage) if

the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has

no # suffix.

845GE Datasheet(PDF) 21 Page - Intel Corporation