845GE datasheet(49/176 Pages) INTEL

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Intel® 82845GE/82845PE Datasheet

3.5.1.3

PCICMD

—PCI Command Register (Device 0)

Address Offset:

04–05h

Default Value:

0006h

Access:

RO, R/W

Size:

16 bits

Since (G)MCH Device 0 does not physically reside on PCI_A, many of the bits are not

implemented.

Bit

Description

15:10

Reserved.

Fast Back-to-Back Enable (FB2B)—RO.

Hardwired to 0. This bit controls whether or not the master

can do fast back-to-back write. Since Device 0 is strictly a target, this bit is not implemented.

SERR Enable (SERRE)—R/W.

This bit is a global enable bit for Device 0 SERR messaging. The

(G)MCH does not have an SERR signal. The (G)MCH communicates the SERR condition by

sending an SERR message over HI to the Intel® ICH4.

0 = Disable. The (G)MCH does not generate the SERR message for Device 0.

1 = Enable. (G)MCH is enabled to generate SERR messages over the hub interface for specific

Device 0 error conditions that are individually enabled in the ERRCMD register. The error status

is reported in the ERRSTS and PCISTS registers.

NOTE:

This bit only controls SERR messaging for the Device 0. Devices 1has its own SERRE bits

to control error reporting for error conditions occurring on their respective devices. The

control bits are used in a logical OR manner to enable the SERR HI message mechanism.

Address/Data Stepping Enable (ADSTEP)—RO.

Hardwired to 0. Not implemented.

Parity Error Enable (PERRE)—RO.

Hardwired to 0. PERR# is not implemented by the (G)MCH.

VGA Palette Snoop Enable (VGASNOOP)—RO.

Hardwired to 0. Not implemented.

Memory Write and Invalidate Enable (MWIE)—RO.

Hardwired to 0. The (G)MCH will never issue

memory write and invalidate commands.

Special Cycle Enable (SCE)—RO.

Hardwired to 0. The (G)MCH does not implement this bit.

Bus Master Enable (BME)—RO.

Hardwired to 1. The (G)MCH is always enabled as a master on the

hub interface.

Memory Access Enable (MAE)—RO.

Hardwired to 1. Not implemented. The (G)MCH always

allows access to main memory.

I/O Access Enable (IOAE)—RO.

Hardwired to 0. Not implemented.

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