 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SC220 Datasheet(PDF) 19 Page - Zarlink Semiconductor Inc |
|
|
|||||||||||||||||||||||||||||
SC220 Datasheet(HTML) 19 Page - Zarlink Semiconductor Inc |
|
|
19 / 34 page  PRELIMINARY INFORMATION XpressFlow-2020 Series – SC220 Ethernet Switch Chipset XpressFlow Engine © 1998 Vertex Networks, Inc. 18 Rev. 4.5 – February 1999 2.3.5 Register Map Note: All 32-bit registers are D-word aligned. All 16-bit registers are also D-word aligned and right justified. For the Little Endian CPUs, register offset bit [1,0] are always set to be 00. For the Big Endian CPUs, register offset bit [1,0] are always set to be 10. This is a Global Register. CPU is allowed to write the Global Register of all devices by a single operation. These registers are reserved for system diagnostic usage only. I/O Offset Register Description Little Endian Big Endian Reg. Size W/R Note: Device Configuration Registers (DCR) GCR Global Control Register hF00 hF02 16-bit W/-- DCR0 Device Status Register hF00 hF02 16-bit --/R DCR1 Signature & Revision Register hF10 hF12 16-bit --/R DCR2 ID Register hF20 hF22 16-bit W/R DCR3 Local Control Register hF30 hF32 16-bit W/R DCR4 Interface Status Register hF40 hF42 16-bit --/R DCR5 Bus Credit Register hF50 hF52 16-bit W/R Interrupt Controls ISR Interrupt Status Register – Unmasked hF80 hF82 16-bit --/R ISRM Interrupt Status Register – Masked hF90 hF92 16-bit --/R IMSK Interrupt Mask Register hFA0 hFA2 16-bit W/R IAR Interrupt Acknowledgment Register hFB0 hFB2 16-bit W/-- Buffer Memory Interface MWAR Memory Write Address Register – Single Cycle hE08 hE08 32-bit W/R MRAR Memory Read Address Register – Single Cycle hE18 hE18 32-bit W/R MBAR Memory Address Register – Burst Mode hE28 hE28 32-bit W/R MWBS Memory Write Burst Size (in D-words) hE40 hE42 16-bit W/R MRBS Memory Read Burst Size (in D-words) hE50 hE52 16-bit W/R MWDR Memory Write Data Register hE68 hE68 32-bit W/-- MWDX Memory Write Data Register – Byte Swapping hE6C hE6C 32-bit W/-- MRDR Memory Read Data Register hE68 hE68 32-bit --/R MRDX Memory Read Data Register – Byte Swapping hE6C hE6C 32-bit --/R Buffers & Stacks Management Frame Control Buffers FCBBA Frame Control Buffer – Base Address hD00 hD02 16-bit W/R FCBA Frame Control Buffer – Buffer Allocation hD20 hD22 16-bit --/R FCBR Frame Control Buffer – Buffer Release hD20 hD22 16-bit W/-- FCBAG Frame Control Buffer – Buffer Aging Status hD30 hD32 16-bit --/R FCBSA Frame Ctrl Buffer Stack – Base Address hD80 hD82 16-bit W/R FCBSL Frame Ctrl Buffer Stack – Size Limit hD90 hD92 16-bit W/R FCBST Frame Ctrl Buffer Stack – Buffer Low Threshold hDA0 hDA2 16-bit W/R FCBSS Frame Ctrl Buffer Stack – Allocation Status hDB0 hDB2 16-bit --/R |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
