SC220 datasheet(21/34 Pages) ZARLINK

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PRELIMINARY

INFORMATION

XpressFlow-2020 Series –

SC220

Ethernet Switch Chipset

XpressFlow Engine

Rev. 4.5 – February

1999

2.4

XpressFlow Bus Interface

t Vertex Networks’ optimized XpressFlow Bus

architecture

t Provides 1G bps switching bandwidth

t Full multi bus master structure

t Allows XpressFlow Engine to communicate

with Access Controllers via a message pass-

ing protocol

◊ Command Messages for passing control

information between devices

◊ Data Messages for forwarding an Ethernet

frame from receiving port to transmission

port

t Built-in intelligent bus load regulator for data

traffic balancing

t Provides centralized bus arbitration with two

level request priorities

◊ High priority for Data Messages

◊ Low priority for Command Messages

2.4.1 Pin Description

Symbol

Type

Name & Functions

S_D[31:0]

CMOS

I/O-TS

Data Bus Bit [31:0] – a 32-bit synchronous data bus.

Note: During the system RESET period, Data Bit [31:28] are used as

Processor Interface Configuration bit [0:3]

S_MSGEN#

CMOS

I/O-TS

Message Envelope – encompasses the entire period of a message

transfer. Targets use the leading edge of this signal to detect the be-

ginning of a message transfer, and to decode the message header for

the intended target(s).

S_EOF#

CMOS

I/O-TS

End of Frame – only used by frame data transfer messages to identify

the end of frame condition. This signal is synchronous with the Rx

Frame Status word appended to the end of the message.

S_IRDY

CMOS

I/O-TS

Initiator Ready – a normal true signal. When negated, it indicates the

initiator had asserted wait state(s) in between command words. Target

should use this signal as enable signal for latching the data from the

bus.

S_TABT#

CMOS

I/O-OD

Target Abort – when asserted, the target had aborted the reception of

current message on the bus.

S_HPREQ#

CMOS

I/O-OD

High Priority Request – indicates one or more Bus Requester is re-

questing for high priority message transfer.

S_REQ[8:1]#

CMOS

Input

Bus Request [8:1] – Bus Request signals from Access Controllers to

Bus Access Arbitrator in XpressFlow Engine

S_GNT[8:1]#

CMOS

Output

Bus Grant [8:1] – Bus Grant signals from Bus Arbitrator to Bus Re-

questers

S_OVLD#

CMOS

Output

Bus Overload – when asserted all data forwarding bus bandwidth has

been allocated. Cannot support additional load for data forwarding traf-

fic

S_CLK

CMOS

Input

XpressFlow Bus Clock – 33MHz system clock

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