TMS320VC5502 datasheet(22/195 Pages) TI1

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008

www.ti.com

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

Parallel Port — Data Bus

The D[31:16] pins of the Parallel Port serve one of two functions: parallel

general-purpose input/output (PGPIO) signals PGPIO[19:4] or external memory

interface (EMIF) data bus signals EMIF.D[31:16]. The function of the D[31:16] pins is

determined by the state of the GPIO6 pin during reset. The D[31:16] pins are set to

PGPIO[19:4] if GPIO6 is low during reset. The D[31:16] pins are set to

EMIF.D[31:16] if GPIO6 is high during reset. The function of the D[31:16] pins will be

set once the device is taken out of reset (RESET pin transitions from a low to high

D[31:16]

I/O/Z

state).

The D[31:16] bus includes bus holders to reduce the static power dissipation caused

C, D, E, F,

by floating, unused pins. The bus holders also eliminate the need for external bias

G, H, M

resistors on unused pins. When the bus goes into a high-impedance state, the bus

holders keep the data bus at the logic level that was most recently driven. The bus

holders are enabled at reset and can be enabled/disabled through the External Bus

Control Register (XBCR).

Parallel general-purpose I/O. PGPIO[19:4] is selected when GPIO6 is low during

PGPIO[19:4]

I/O/Z

reset. The PGPIO[19:4] signals are configured as inputs after reset.

EMIF data bus. EMIF.D[31:16] is selected when GPIO6 is high during reset. The

EMIF.D[31:16]

I/O/Z

EMIF.D[31:16] signals are configured as inputs after reset.

The D[15:0] pins of the Parallel Port serve one of two functions: host-port interface

(HPI) data bus signals HPI.HD[15:0] and external memory interface (EMIF) data bus

signals EMIF.D[15:0]. The function of the D[15:0] pins is determined by the state of

the GPIO6 pin during reset. The D[15:0] pins are set to HPI.HD[15:0] if GPIO6 is low

during reset. The D[15:0] pins are set to EMIF.D[15:0] if GPIO6 is high during reset.

The function of the D[15:0] pins will be set once the device is taken out of reset

D[15:0]

I/O/Z

(RESET pin transitions from a low to high state).

The D[15:0] bus includes bus holders to reduce the static power dissipation caused

by floating, unused pins. The bus holders also eliminate the need for external bias

resistors on unused pins. When the bus goes into a high-impedance state, the bus

C, D, E, F, holders keep the data bus at the logic level that was most recently driven. The bus

holders are enabled at reset and can be enabled/disabled through the External Bus

Control Register (XBCR).

HPI data bus. HPI.HD[15:0] is selected when GPIO6 is low during reset. The

HPI.HD[15:0] signals are configured as inputs after reset.

The HPI will operate in non-multiplexed mode when GPIO6 is low during reset. In

HPI.HD[15:0]

I/O/Z

non-multiplexed mode, the HPI uses separate address and data buses: a 16-bit

address bus (HPI.HA[15:0]) and a 16-bit data bus (HPI.HD[15:0]). Each host cycle

on the data bus consists of one 16-bit data transfer.

EMIF data bus. EMIF.D[15:0] is selected when GPIO6 is high during reset. The

EMIF.D[15:0]

I/O/Z

EMIF.D[15:0] signals are configured as inputs after reset.

Parallel Port — Control Pins

The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO20 or external memory interface control signal

EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the

I/O/Z

state of the GPIO6 pin during reset. The C0 pin is set to PGPIO20 if GPIO6 is low

during reset. The C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high

during reset. The function of the C0 pin will be set once the device is taken out of

reset (RESET pin transitions from a low to high state).

Parallel general-purpose I/O. PGPIO20 is selected when GPIO6 is low during

PGPIO20

I/O/Z

C, D, E, F,

reset. The PGPIO20 signal is configured as an input after reset.

G, H, M

EMIF control pin. EMIF.ARE/SADS/SDCAS/SRE is selected when GPIO6 is high

during reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state

during reset and is set to output after reset with an output value of 1.

EMIF.ARE/

The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used

SADS/SDCAS/

O/Z

by the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory

SRE

address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and

synchronous read-enable (EMIF.SRE) (selected by RENEN in the CE Secondary

Control Register 1).

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