TMS320VC5502 datasheet(72/195 Pages) TI1

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3.11.1

Clock Domains

3.11.2

IDLE Procedures

3.11.2.1 CPU Domain Idle Procedure

3.11.2.2 Master Port Domain (DMA/HPI) Idle Procedure

3.11.2.3 Peripheral Modules Idle Procedure

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008

www.ti.com

The 5502 provides six clock domains to power-off the main clock to the portions of the device that are not

being used. The six domains are:

• CPU Domain

• Master Port Domain (includes DMA and HPI modules)

• ICACHE

• Peripherals Domain

• Clock Generator Domain

• EMIF Domain

Before entering idle mode (executing the IDLE instruction), the user has first to determine which part of

the system needs to be disabled and then program the Idle Control Register (ICR) accordingly. When the

IDLE instruction is executed, the ICR will be copied into the Idle Status Register (ISTR). The different bits

of the ISTR register will be propagated to disable the chosen domains. Special care has to be taken in

programming the ICR as some IDLE domain combinations are not valid (for example: CPU on and clock

generator off).

The 5502 CPU can be idled by executing the following procedure.

1. Write '1' to the CPUI bit (bit 0 of ICR).

2. Execute the IDLE instruction.

3. CPU will go to idle state

The clock to the DMA module and/or the HPI module will be stopped when the DMA and/or the HPI bit in

the MICR is set to 1 and the MPIS bit in the ISTR becomes 1. The DMA will go into idle immediately if

there is no data transfer taking place. If there is a data transfer taking place, then it will finish the current

transfer and then go into idle. The HPI will go into idle regardless of whether or not there is a data transfer

taking place. Software must confirm that the HPI has no activity before setting it to idle.

The 5502 DMA module and the HPI module can be disabled by executing the following procedure.

1. Write '1' to the DMA bit and/or the HPI bit in MICR.

2. Write '1' to the MPI bit in ICR.

3. Execute the IDLE instruction.

4. DMA and/or HPI go/goes to idle.

The clock to the modules included in the Peripherals Domain will be stopped when their corresponding bit

in the PICR is set to 1 and the PERIS bit in the ISTR becomes 1. Each module in this domain will go into

idle immediately if it has no activity. If the module being set to idle has activity, it will wait until the activity

completes before going into idle.

Each peripheral module can be idled by executing the following procedure.

1. Write '1' to the corresponding bit in PICR for each peripheral to be idled.

2. Write '1' to the PERI bit in ICR.

3. Execute the IDLE instruction.

4. Every peripheral with its corresponding PICR bit set will go to idle.

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