VSC7511 datasheet(206/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

191

Software can abort frames by writing to injection status with ABORT field set. All other status word fields

are ignored. When a frame is aborted, the already injected data is removed from the queuing system.

4.8

VCore-Ie System Peripherals

This section describes the subblocks of the VCore-Ie system. Although the subblocks are primarily

intended to be used by the VCore-Ie CPU, an external CPU can also access and control them through

the shared bus.

4.8.1

SI Boot Controller

The SPI boot master allows booting from a Flash that is connected to the serial interface. For information

about how to write to the serial interface, see SI Master Controller, page 193. For information about using

an external CPU to access device registers using the serial interface, see Serial Interface in Slave Mode,

page 170.

The following table lists the registers associated with the SI boot controller.

By default, the SI boot controller operates in 24-bit address mode. In this mode, there are four

programmable chip selects when the VCore-Ie system controls the SI. Each chip select can address up

to 16 megabytes (MB) of memory.

Figure 71 •

SI Boot Controller Memory Map in 24-Bit Mode

The SI boot controller can be reconfigured for 32-bit address mode through SPI_MST_CFG.A32B_ENA.

In 32-bit mode, the entire SI region of 256 megabytes (MB) is addressed using chip select 0.

Figure 72 •

SI Boot Controller Memory Map in 32-Bit Mode

Reading from the memory region for a specific SI chip select generates an SI read on that chip select.

The VCore-Ie CPU can execute code directly from Flash by executing from the SI boot controller’s

memory region. For 32-bit capable SI Flash devices, the VCore-Ie must start up in 24-bit mode. During

the boot process, it must manually reconfigure the Flash device (and SI boot controller) into 32-bit mode

and then continue booting.

The SI boot controller accepts 8-bit, 16-bit, and 32-bit read access with or without bursting. Writing to the

SI requires manual control of the SI pins using software. Setting SW_MODE.SW_PIN_CTRL_MODE

Table 150 •

SI Boot Controller Configuration Registers

Description

ICPU_CFG::SPI_MST_CFG

Serial interface speed and address width

ICPU_CFG::SW_MODE

Legacy manual control of the serial interface pins

ICPU_CFG::GENERAL_CTRL

SI interface ownership

SI Controller Memory Map

Chip Select 0, SI_nCS0

SI Controller

16 MB

Chip Select 1, SI_nCS1

+0x01000000

16 MB

Chip Select 2, SI_nCS2

16 MB

Chip Select 3, SI_nCS3

16 MB

+0x02000000

+0x03000000

SI Controller Memory Map (32- bit)

Chip Select 0, SI_nCS0

SI Controller

256 MB

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