VSC7511 datasheet(208/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

193

Calculate an appropriate frequency divider value as described in SPI_MST_CFG.CLK_DIV. The SI

operates at no more than 25 MHz, and the maximum frequency of the SPI device must not be

exceeded. The VCore-Ie system frequency in the device is 250 MHz.

The SPI device may require a FAST_READ command rather than normal READ when the SI

frequency is increased. Setting SPI_MST_CFG.FAST_READ_ENA makes the SI boot controller use

FAST_READ commands.

Calculate SPI_MST_CFG.CS_DESELECT_TIME so that it matches how long the SPI device

requires chip-select to be deasserted between access. This value depends on the SI clock period

that results from the SPI_MST_CFG.CLK_DIV setting.

These parameters must be written to SPI_MST_CFG. The CLK_DIV field must either be written last or at

the same time as the other parameters. The SPI_MST_CFG register can be configured while also

booting up from the SI.

When the VCore-Ie CPU boots from the SI interface, the default values of the SPI_MST_CFG register

are used until the SI_MST_CFG is reconfigured with optimized parameters. This implies that SI_CLK is

operating at approximately 8.1 MHz, with normal read instructions and maximum gap between chip

select operations to the Flash.

Note The SPI boot master does optimized reading. SI_DI (from the Flash) is sampled just before

driving falling edge on SI_CLK (to the Flash). This greatly relaxes the round trip delay requirement for

SI_CLK to SI_DI, allowing high Flash clock frequencies.

4.8.2

SI Master Controller

This section describes the SPI master controller (SIMC) and how to use it for accessing external SPI

slave devices, such as programming of a serially attached Flash device on the boot interface. VCore

booting from serial Flash is handled by the SI boot master.

The following table lists the registers associated with the SI master controller.

Table 152 •

SI Master Controller Configuration Registers Overview

Description

SIMC::CTRLR0

Transaction configuration

SIMC::CTRLR1

Configurations for receive-only mode

SIMC::SIMCEN

SI master controller enable

SIMC::SER

Slave select configuration

SIMC::BAUDR

Baud rate configuration

SIMC::TXFTLR

Tx FIFO threshold level

SIMC::RXFTLR

Rx FIFO Threshold Level

SIMC::TXFLR

Tx FIFO fill level

SIMC::RXFLR

Rx FIFO fill level

SIMC::SR

Various status indications

SIMC::IMR

Interrupt enable

SIMC::ISR

Interrupt sources

SIMC::RISR

Unmasked interrupt sources

SIMC::TXOICR

Clear of transmit FIFO overflow interrupt

SIMC::RXOICR

Clear of receive FIFO overflow interrupt

SIMC::RXUICR

Clear of receive FIFO underflow interrupt

SIMC::DR

Tx/Rx FIFO access

SIMC::RX_SAMPLE_DLY

RXD sample delay

ICPU_CFG::GENERAL_CTRL

Interface configurations

VSC7511 Datasheet(PDF) 208 Page - Microsemi Corporation

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