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VSC7511 Datasheet(PDF) 207 Page - Microsemi Corporation

Part # VSC7511
Description  4-Port Layer-2 Gigabit Ethernet Switch
PDF  324 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7511 Datasheet(HTML) 207 Page - Microsemi Corporation

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VCore-Ie System and CPU Interfaces
VMDS-10488 VSC7511 Datasheet Revision 4.2
192
places all SI pins under software control. Output enable and the value of SI_CLK, SI_DO, SI_nCSn are
controlled through the SW_MODE register. The value of the SI_DI pin is available in
SW_MODE.SW_SPI_SDI. The software control mode is provided for legacy reasons; new
implementations should use the dedicated master controller for writing to the serial interface. For more
information see SI Master Controller, page 193.
Note The VCore-Ie CPU cannot execute code directly from the SI boot controller’s memory region at
the same time as manually writing to the serial interface.
The following table lists the serial interface pins when the SI boot controller is configured as owner of SI
interface in GENERAL_CTRL.IF_SI_OWNER. For more information about overlaid functions on the
GPIOs for these signals, see GPIO Overlaid Functions, page 204.
The SI boot controller does speculative pre-fetching of data. After reading address n, the SI boot
controller automatically continues reading address n + 1, so that the next value is ready if requested by
the VCore-Ie CPU. This greatly optimizes reading from sequential addresses in the Flash, such as when
copying data from Flash into program memory.
The following illustrations depict 24-bit address mode. When the controller is set to 32-bit mode (through
SPI_MST_CFG.A32B_ENA), 32 address bits are transferred instead of 24.
Figure 73 •
SI Read Timing in Normal Mode
Figure 74 •
SI Read Timing in Fast Mode
The default timing of the SI boot controller operates with most serial interface Flash devices. Use the
following process to calculate the optimized serial interface parameters for a specific SI device:
Table 151 •
Serial Interface Pins
Pin Name
I/O
Description
SI_nCS0
SI_nCS[3:1]/GPIO
O
Active low chip selects. Only one chip select can be active at any
time. Chip selects 1 through 3 are overlaid functions on GPIO pins.
SI_CLK
O
Clock output.
SI_DO
O
Data output (MOSI).
SI_DI
I
Data input (MISO).
SI_nCS0
SI_CLK
SI_DO
SI_DI
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9876543210
READ
543210
6
7
Data Byte #0
2
3
2
2
24 Bit Address
543210
6
7
Data Byte #1
543210
6
7
Data Byte #2
543210
6
7
Data Byte #3
SI_nCS0
SI_CLK
SI_DO
SI_DI
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 98 765 43 2 1 0
FAST_READ
5 432 10
6
7
Data Byte #0
2
3
2
2
24 Bit Address
5 432 10
6
7
Data Byte #1
5 432 10
6
7
Data Byte #2
54 3 210
6
7
Data Byte #3
Dummy Byte



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