PMS150C datasheet(66/67 Pages) PADAUK

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PMS150C

8 bit IO-Type Controller

Page 66 of 67

PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018

9.2.7. LVR

(1) VDD must reach or above 2.0V for successful power-on process; otherwise IC will be inactive.

(2) The setting of LVR (1.8V ~ 4.0V) will be valid just after successful power-on process.

(3) User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working

voltage of chip; Otherwise IC may work abnormally.

9.2.8. Instructions

(1) There are 79 instructions are provided by PMS150C.

(2) Only single FPPA is built inside the PMS150C, the executing cycles for different instructions are shown as

below:

Instruction

Condition

CPU

goto, call, pcadd, ret, reti

ceqsn, cneqsn, t0sn, t1sn,

dzsn, izsn

Condition is fulfilled

Condition is not fulfilled

idxm

Others

9.2.9. RAM definition

(1)

Bit defined: Only addressed at 0x00 ~ 0x0F

(2)

WORD defined : Only addressed at 0x00 ~ 0x1E

9.2.10. Program writing

There are 6 pins for using the writer to program: PA3, PA4, PA5, PA6, VDD and GND.

Please use PDK3S-P-002 for program real chip and just use the CN38 jumper (at the back for the writer) with

putting the PMS150-S08/DIP8 IC downward three spaces on the Textool . Other packages could be

programmed by connecting the signals correspondingly. All the signals of the left side of the jumpers are the

same and as the descriptions at the left bottom corner. They are VDD, PA0(not used), PA3, PA4, PA5, PA6,

PA7(not used), and GND).

If user use PDK5S-P-003 or above to program, please follow the instructions for connecting jumpers

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