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OPA388 Datasheet(PDF) 21 Page - Texas Instruments

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Part # OPA388
Description  OPA388-Q1 Automotive, Precision, Zero-Drift, Zero-Crossover, True Rail-to-Rail, Input/Output Operational Amplifier
PDF  31 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

OPA388 Datasheet(HTML) 21 Page - Texas Instruments

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8 Power Supply Recommendations
The OPA388-Q1 device is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V). Parameters that can
exhibit significant variance with regard to operating voltage are presented in Section 6.6.
9 Layout
9.1 Layout Guidelines
Paying attention to good layout practice is always recommended. Keep traces short and, when possible, use a
printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as
possible. Place a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout
the analog circuit to improve performance and provide benefits such as reducing the electromagnetic
interference (EMI) susceptibility.
For lowest offset voltage and precision performance, circuit layout and mechanical conditions must be optimized.
Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed
from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring
they are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
9.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 9-1. Schematic Representation
N/C
±IN
+IN
V±
V+
OUTPUT
N/C
N/C
VS+
GND
Ground (GND) plane on another layer
VOUT
VIN
GND
Run the input traces
as far away from
the supply lines
as possible
RF
RG
Place components close
to device and to each
other to reduce parasitic
errors
Use low-ESR,
ceramic bypass
capacitors
GND
Figure 9-2. Layout Example
www.ti.com
OPA388-Q1
SBOS989 – AUGUST 2020
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: OPA388-Q1



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