FT232RL datasheet(11/40 Pages) FTDI

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FT232R USB UART IC Datasheet

Version 2.16

Document No.: FT_000053 Clearance No.: FTDI# 38

3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These

pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an

option in the internal EEPROM.

3.5 CBUS Signal Options

The following options can be configured on the CBUS I/O pins. CBUS signal options are common to both

package versions of the FT232R. These options can be configured in the internal EEPROM using the

software utility FT_PROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com). The

default configuration is described in Section 8.

CBUS Signal

Option

Available On CBUS Pin

Description

TXDEN

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

Enable transmit data for RS485

PWREN#

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

Output is low after the device has been configured

by USB, then high during USB suspending mode.

This output can be used to control power to

external logic P-Channel logic level MOSFET switch.

Enable the interface pull-down option when using

the PWREN# in this way.*

TXLED#

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

Transmit data LED drive: Data from USB Host to

FT232R. Pulses low when transmitting data via USB.

See Section 7.5 for more details.

RXLED#

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

Receive data LED drive: Data from FT232R to USB

Host. Pulses low when receiving data via USB. See

Section 7.5 for more details.

TX&RXLED#

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

LED drive – pulses low when transmitting or

receiving data via USB. See Section 7.5 for more

details.

SLEEP#

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

Goes low during USB suspend mode. Typically used

to power down an external TTL to RS232 level

converter IC in USB to RS232 converter designs.

CLK48

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

48MHz ±0.7% Clock output. **

CLK24

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

24 MHz Clock output. **

CLK12

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

12 MHz Clock output. **

CLK6

CBUS0, CBUS1, CBUS2,

CBUS3, CBUS4

6 MHz ±0.7% Clock output. **

CBitBangI/O

CBUS0, CBUS1, CBUS2,

CBUS3

CBUS bit bang mode option. Allows up to 4 of the

CBUS pins to be used as general purpose I/O.

Configured individually for CBUS0, CBUS1, CBUS2

and CBUS3 in the internal EEPROM. A separate

application note, AN232R-01, available from FTDI

website (www.ftdichip.com) describes in more detail

how to use CBUS bit bang mode.

BitBangWRn

CBUS0, CBUS1

Synchronous and asynchronous bit bang mode WR#

strobe output.

BitBangRDn

CBUS0, CBUS1, CBUS2,

CBUS3

Synchronous and asynchronous bit bang mode RD#

strobe output.

Table 3.9 CBUS Configuration Control

* PWREN# must be used with a 10kΩ resistor pull up.

**When in USB suspend mode the outputs clocks are also suspended.

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