7

U6809B

4764A–AUTO–10/03

WDI Input (Pin 20)

The microcontroller has to provide a trigger signal with the frequency f

the WDI input. A positive edge of f

clocks the up/down counter additionally. The up/down counter only counts from 0 to 3 or

reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger

decrements it by 1. As soon as the counter reaches the count of 3 the RS flip-flop is set

(see Figure 5). A missing incoming trigger signal is detected after 250 clocks of the inter-

nal watchdog frequency f

directly.

RCOSC Input

With an external RC circuitry the IC generates a time base (frequency f

from the microcontroller. The watchdog's time window refers to a frequency of

RC = 100

´ f

WDI

Reset Input

During power-on and under-/overvoltage detection a reset signal is fed to this pin. It

resets the watchdog timer and sets the initial state.

WD - OK Output

After the up/down counter has been incremented to the count of 3 (see Figure 5, WD

state diagram), the RS flip-flop is set and the WD-OK output becomes logic "1". This

information is available for the microcontroller at the open-collector output ENO. If, on

the other hand, the up/down counter is decremented to 0 the RS flip flop is reset, the

WD OK output and the ENO output are disabled. The WD OK output also controls a

dual MUX stage which shifts the time window by one clock after a successful trigger,

thus forming a hysteresis to provide stable conditions for the evaluation of the trigger

signal "good or false". The WD OK signal is also reset in case the watchdog counter is

not reset after 250 clocks (missing trigger signal).

Watchdog State Diagram

Figure 5. Watchdog State Diagram

Explanation

In each block, the first character represents the state of the counter. The second nota-

tion indicates the fault status of the counter. A fault status is indicated by an "F" and a no

fault status is indicated by an "NF". When the watchdog is powered up initially, the

counter starts at the 0/F block (initial state). "Good" indicates that a pulse has been

received whose width resides within the timing window. "Bad" indicates that a pulse has

been received whose width is either too short or too long.

1/NF

2/NF

O/F

1/F

2/F

3/NF

bad

good

bad

good

bad

good

good

bad

good

good

bad

bad

Initial status