July 2005

ASM5I9350

rev 0.2

3.3V 1:10 LVCMOS PLL Clock Generator

4 of 12

Notice: The information in this document is subject to change without notice.

Table 2: Function Table

Control

Default

0

1

REF_SEL

0

Xtal

TCLK

PLL_EN

1

Bypass mode, PLL disabled. The

input clock connects to the output

dividers

PLL enabled. The VCO output connects to

the output dividers

OE#

0

Outputs enabled

Outputs disabled (three-state)

FB_SEL

0

Feedback divider ÷32

Feedback divider ÷16

SELA

0

÷2 (Bank A)

÷ 4 (Bank A)

SELB

0

÷4 (Bank B)

÷ 8 (Bank B)

SELC

0

÷4 (Bank C)

÷ 8 (Bank C)

SELD

0

÷4 (Bank D)

÷ 8 (Bank D)

Absolute Maximum Ratings

Parameter

Description

Condition

Min

Max

Unit

DC Supply Voltage

–0.3

5.5

V

DC Operating Voltage

Functional

2.375

3.465

V

DC Input Voltage

–0.3

V

DC Output Voltage

–0.3

V

Output termination Voltage

V

LU

Latch Up Immunity

Functional

200

mA

Power Supply Ripple

Ripple Frequency < 100 kHz

150

mVp-p

Temperature, Storage

Non-functional

–65

+150

°C

Temperature, Operating Ambient

Functional

–40

+85

°C

Temperature, Junction

Functional

+150

°C

Dissipation, Junction to Case

Functional

42

°C/W

Dissipation, Junction to Ambient

Functional

105

°C/W

ESD Protection (Human Body Model)

2000

Volts

FIT

Failure in Time

Manufacturing test

10

ppm