July 2005

ASM5I9350

rev 0.2

3.3V 1:10 LVCMOS PLL Clock Generator

5 of 12

Notice: The information in this document is subject to change without notice.

Parameter

Description

Condition

Min

Typ

Max

Unit

Input Voltage, Low

LVCMOS

-

-

0.7

V

Input Voltage, High

LVCMOS

1.7

-

V

Output Voltage, Low

1

-

-

0.6

V

Output Voltage, High

1

1.8

-

-

V

Input Current, Low

2

-

-

-100

µA

Input Current, High

2

-

-

100

µA

PLL Supply Current

AVDD only

-

5

10

mA

Quiescent Supply Current

All VDD pins except AVDD

-

-

7

mA

Outputs loaded @ 100 MHz

-

180

-

Dynamic Supply Current

Outputs loaded @ 200 MHz

-

210

-

mA

Input Pin Capacitance

-

4

-

pF

Output Impedance

14

18

22

Ω

transmission lines.

2. Inputs have pull-up or pull-down resistors that affect the input current.

Parameter

Description

Condition

Min

Typ

Max

Unit

Input Voltage, Low

LVCMOS

-

-

0.8

V

Input Voltage, High

LVCMOS

2.0

-

V

-

-

0.55

Output Voltage, Low

1

-

-

0.30

V

Output Voltage, High

1

2.4

-

-

V

Input Current, Low

2

-

-

–100

µA

Input Current, High

2

-

-

100

µA

PLL Supply Current

AVDD only

-

5

10

mA

Quiescent Supply Current

All VDD pins except AVDD

-

-

7

mA

Outputs loaded @ 100 MHz

-

270

-

Dynamic Supply Current

Outputs loaded @ 200 MHz

-

300

-

mA

Input Pin Capacitance

-

4

-

pF

Output Impedance

12

15

18

Ω

Note: 1. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated

transmission lines.

2. Inputs have pull-up or pull-down resistors that affect the input current.