DLP471TP datasheet(32/48 Pages) TI

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD:

• VSS

• VBIAS

• VDD

• VDDA

• VOFFSET

• VRESET

DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to any of the prescribed power-up and power-down requirements may

affect device reliability. See the DMD power supply sequencing requirements in Figure 9-1.

VBIAS, VDD, VDDA, VOFFSET, and VRESET power supplies must be coordinated during power-up and

power-down operations. Failure to meet any of the below requirements will result in a significant

reduction in the DMD reliability and lifetime. Common ground VSS must also be connected.

Table 9-1. Power Supply Sequence Requirements

SYMBOL

PARAMETER

DESCRIPTION

MIN

TYP

MAX UNIT

tDELAY

Delay requirement

from VOFFSET power up to VBIAS power up

VOFFSET

Supply voltage level

at beginning of power-up sequence delay(1)

VBIAS

Supply voltage level

at end of power-up sequence delay(1)

(1)

See Figure 9-1, Power-Up Sequence Delay Requirement.

9.1 DMD Power Supply Power-Up Procedure

• During power-up, VDD and VDDA must always start and settle before VOFFSET plus Delay1 specified in Table

9-2, VBIAS, and VRESET voltages are applied to the DMD.

• During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be

within the specified limit shown in Section 6.4.

• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.

• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.

• During power-up, LVCMOS input pins must not be driven high until after VDD have settled at operating

voltages listed in Section 6.4.

9.2 DMD Power Supply Power-Down Procedure

• During power-down, VDD and VDDA must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to

within the specified limit of ground. See Table 9-2.

• During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be

within the specified limit shown in Section 6.4.

• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements specified in Section 6.1, inSection 6.4, and in Figure 9-1.

• During power-down, LVCMOS input pins must be less than specified in Section 6.4.

DLP471TP

DLPS173 – AUGUST 2020

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