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DLP471TP Datasheet(PDF) 13 Page - Texas Instruments |
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DLP471TP Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 48 page ![]() 6.7 Switching Characteristics Over operating free-air temperature range and supply voltages (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tpd Output propagation, Clock to Q (C2Q), rising edge of LS_CLK (differential clock signal) input to LS_RDATA output. (1) CL = 5 pF 11.1 ns CL = 10 pF 11.3 ns Slew rate, LS_RDATA 20%-80%, CL <10pF 0.5 V/ns Output duty cycle distortion, LS_RDATA_A and LS_RDATA_B 50-(C2Q rise - C2Q fall )*130e6*100 40 60 % (1) See Figure 6-2. Stop (1) LS_WDATA_P Start (0) LS_CLK_P LS_RDATA_A BIST_A LS_CLK_N LS_WDATA_N Acknowledge tPD 0 1 1 0 1 1 period 0 1 0 1 0 Figure 6-2. Switching Characteristics www.ti.com DLP471TP DLPS173 – AUGUST 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 |
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