LMK04832WSLASHEM datasheet(39/99 Pages) TI

39 / 99 page

8.4.3 Distribution Mode

Figure 8-15 illustrates the use case of distribution mode. As in all the other use cases, OSCin to OSCout can be

used as a buffer to OSCin or from clock distribution path through CLKout6, CLKout8, or the SYSREF divider.

At high frequency, the input impedance to Fin0/Fin1 is low and a resistive pad is recommended for matching.

Fin0

Fin0*

OSCout

OSCout*

CLKoutY

CLKoutY*

CLKoutX

CLKoutX*

7 blocks

Device Clock

Divider

Digital Delay

SYSREF

Digital Delay

Analog Delay

Global SYSREF

Divider and DDLY

CLKin0

CLKin0*

OSCin

OSCin*

CLKout6/8

Fin1

Fin1*

Figure 8-15. Simplified Functional Block Diagram for Distribution Mode

8.5 Programming

The LMK04832 device is programmed using 24-bit registers. Each register consists of a 1-bit command field

(R/W), a 15-bit address field (A14 to A0) and a 8-bit data field (D7 to D0). The contents of each register is

clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial

data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to

latch the contents into the shift register. TI recommends to program registers in numeric order (for example,

0x000 to 0x555 with exceptions noted in the Section 8.5.1). Each register consists of one or more fields which

control the device functionality. See the Section 6.5 section and Figure 6-1 for timing details.

8.5.1 Recommended Programming Sequence

Registers are generally programmed in numeric order with 0x000 being the first and 0x555 being the last register

programmed. The recommended programming sequence from POR involves:

1. Program register 0x000 with RESET = 1.

2. Program defined registers from 0x000 to 0x165.

3. If PLL2 is used, program 0x173 with PLL2_PD and PLL2_PRE_PD clear to allow PLL2 to lock after PLL2_N

is programmed.

4. Continue programming defined registers from 0x166 to 0x555.

Note

When using the internal VCO, PLL2_N registers 0x166, 0x167, and 0x168 must be programmed after

other PLL2 dividers are programed to ensure proper VCO frequency calibration. This is also true for

PLL2_N_CAL registers 0x163, 0x164, 0x165 when PLL2_NCLK_MUX = 1. So if any divider such as

PLL2_R is altered to change the VCO frequency, the VCO calibration must be run again by

programming PLL2_N.

Power up PLL2 by setting PLL2_PRE_PD = 0 and PLL2_PD = 0 in register 0x173 before

programming PLL2_N.

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LMK04832-SP

SNAS698A – MARCH 2017 – REVISED AUGUST 2020

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