EM78P803A

8-bit Micro-controller

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* This specification are subject to be changed without notice.

9

2005/8/12

V1.3.3

VII. Functional Descriptions

VII.1 Operational Registers

Register configuration 1:

IOC PAGE

Addr

R PAGE registers

IOC PAGE0

IOC PAGE1

00

INDA

Indirect addressing

01

TCCD

TCC data

02

PC

Program counter

03

STA

IOC Page, Tone 1, 2 power control,

Status

04

RBSR

Register bank, RSR

05

P5IOD

PORT5 I/O data, Program ROM page

P5IOC

PORT5 I/O control,

06

P6IOD

PORT6 I/O data

P6IOC

PORT6 I/O control

07

P7IOD

PORT7 I/O data

P7IOC

PORT7 I/O control

08

P8IOD

PORT8 I/O date

P8IOC

PORT8 I/O control

09

P9IOD

PORT9 I/O data

P9IOC

PORT9 I/O control

0A

MCUC

CPU power saving, PLL, Main clock

selection

PSW

(P8 low nibble, P5) switch, LCD bias, Key

scan control

DEDC

LCD power saving, Low battery detect,

DED control

0B

DEDO

Green tone, DED output, CID RAM

bank

LCDA

LCD RAM address

CN1D

Counter 1 data

0C

RAMA

CID RAM address

LCDD

LCD RAM data

CN2D

Counter 2 data

0D

RAMD

CID RAM data

TONE1C

TONE1 control

P7PHC

PORT7 pull high

0E

WUPC

Wake-up control, LCD control

TONE2C

TONE2 control

CNPSC

Open Drain Control, CNT1,2 CLK source,

CNT1,2 prescaler, LCD mode

0F

INTF

Interrupt flag

INTM

Interrupt mask

10

:

1F

16 bytes

Common registers

20

:

3F

Common registers

(32x8 for each bank)

Ps. 1. Register 20~3F has bank0~bank2 only. The bank3 doesn’t exist and cannot access it.