PFS173 datasheet(73/105 Pages) PADAUK

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PFS173

8bit MTP MCU with 8-bit ADC

Page 73 of 105

PDK-DS-PFS173-EN_V105-Jun. 19, 2020

6.22. Port C Pull-Low Register (pcpl), IO address = 0x1a

Bit

Reset

R/W

Description

7 - 2

Reserved.

R/W

Port PC1 pull-low register.

0 / 1 : disable / enable

R/W

Port PC0 pull-low register.

0 / 1 : disable / enable

6.23. ADC Control Register (adcc), IO address = 0x20

Bit

Reset

R/W

Description

R/W

Enable ADC function. 0/1: Disable/Enable.

R/W

ADC process control bit.

Write “1” to start conversion

Read “1” to indicate the ADC is ready or end of conversion.

5 - 2

0000

R/W

Channel selector. These four bits are used to select input signal for AD conversion.

0000: PB0/AD0,

0001: PB1/AD1,

0010: PB2/AD2,

0011: PB3/AD3,

0100: PB4/AD4,

0101: PB5/AD5,

0110: PB6/AD6,

0111: PB7/AD7,

1000: PA3/AD8,

1001: PA4/AD9,

1010: PA0/AD10,

1011: PC1/AD11, (PA1 for ICE at this address)

1100: PC2/AD12, (PC1 for ICE at this address)

1111: (Channel F) Band-gap reference voltage

Others: reserved

0 - 1

Reserved. (keep 0 for future compatibility)

6.24. ADC Mode Register (adcm), IO address = 0x21

Bit

Reset

R/W

Description

7 - 4

Reserved. (keep 0 for future compatibility)

3 - 1

000

R/W

ADC clock source selection.

000: CLK (system clock) ÷ 1,

001: CLK (system clock) ÷ 2,

010: CLK (system clock) ÷ 4,

011: CLK (system clock) ÷ 8,

100: CLK (system clock) ÷ 16,

101: CLK (system clock) ÷ 32,

110: CLK (system clock) ÷ 64,

111: CLK (system clock) ÷ 128,

Reserved.

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