PFS173 datasheet(77/105 Pages) PADAUK

77 / 105 page

PFS173

8bit MTP MCU with 8-bit ADC

Page 77 of 105

PDK-DS-PFS173-EN_V105-Jun. 19, 2020

6.33. Timer2 Bound Register (tm2b), IO address = 0x33

Bit

Reset

R/W

Description

7 - 0

0x00

Timer2 bound register.

6.34. Timer3 Control Register (tm3c), IO address = 0x34

Bit

Reset

R/W

Description

7 - 4

0000

R/W

Timer3 clock selection.

0000 : disable

0001 : CLK

0010 : IHRC or IHRC *2 (by code option TMx_source)

0011 : EOSC

0100 : ILRC

0101 : comparator output

1000 : PA0 (rising edge)

1001 : ~PA0 (falling edge)

1010 : PB0 (rising edge)

1011 : ~PB0 (falling edge)

1100 : PA4 (rising edge)

1101 : ~PA4 (falling edge)

Others: reserved

Notice: In ICE mode and IHRC is selected for Timer3 clock, the clock sent to Timer3 does

NOT be stopped, Timer3 will keep counting when ICE is in halt state.

3 - 2

R/W

Timer3 output selection.

00 : disable

01 : PB5

10 : PB6

11 : PB7

R/W

Timer3 mode selection.

0 / 1 : period mode / PWM mode

R/W

Enable to inverse the polarity of Timer3 output.

0 / 1: disable / enable

6.35. Timer3 Counter Register (tm3ct), IO address = 0x35

Bit

Reset

R/W

Description

7 - 0

0x00

R/W

Bit [7:0] of Timer2 counter register.

PFS173 Datasheet(PDF) 77 Page - PADAUK Technology.

PFS173 Datasheet(HTML) 77 Page - PADAUK Technology.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL