PFS173 datasheet(78/105 Pages) PADAUK

78 / 105 page

PFS173

8bit MTP MCU with 8-bit ADC

Page 78 of 105

PDK-DS-PFS173-EN_V105-Jun. 19, 2020

6.36. Timer3 Scalar Register (tm3s), IO address = 0x36

Bit

Reset

R/W

Description

PWM resolution selection.

0 : 8-bit

1 : 6-bit or 7-bit (by code option TMx_bit)

6 - 5

Timer3 clock pre-scalar.

00 : ÷ 1

01 : ÷ 4

10 : ÷ 16

11 : ÷ 64

4 - 0

00000

Timer3 clock scalar.

6.37. Timer3 Bound Register (tm3b), IO address = 0x37

Bit

Reset

R/W

Description

7 - 0

0x00

Timer3 bound register.

6.38. PWMG0 control Register (pwmg0c), IO address = 0x40

Bit

Reset

R/W

Description

Reserved.

Output status of PWMG0 generator.

Enable to inverse the polarity of PWMG0 generator output. 0 / 1: disable / enable.

PWMG0 output selection.

0: PWMG0 Output

1: PWMG0 XOR PWMG1 or PWMG0 OR PWMG1 (by pwmg0c.0)

3 - 1

000

R/W

PWMG0 Output Port Selection

000: PWMG0 Output Disable

001: PWMG0 Output to PB5

010: PWMG0 Output to PC2

011: PWMG0 Output to PA0

100: PWMG0 Output to PB4

101: PWMG0 Output to PB6 (Available if the PB6 is not assigned to output PWMG1)

others: Reserved

R/W

PWMG0 output pre- selection.

0: PWMG0 XOR PWMG1

1: PWMG0 OR PWMG1

PFS173 Datasheet(PDF) 78 Page - PADAUK Technology.

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