NJW1504/1508

- 5 -

n I

The input information, which consists of chip address and next two or four byte data, is received by I

receiver. The allowable I

(1) STA CA CB BB STO

(2) STA CA D1 D2 STO

(3) STA CA CB BB D1 D2 STO

(4) STA CA D1 D2 CB BB STO

STA: Start Condition

STO: Stop Condition

CA: Chip Address

CB: Control Byte

BB: Band switch Byte

D1: Divider Byte 1

D2: Divider Byte 2

For suitable circuit operation,5-byte data should have chip address, 2-byte control data, band data, and 2-byte

divider byte. Following chip address. 2-byte data is received. For distinction of each data, first and third data

byte has a function bit. As function bit, divider byte has “1” and control/band data has “0”.

1-7

9

S DA

SCL

STA

ADDRESS

R/W

1 -7

ACK

DATA

8

8

9

9

ACK

ACK

STO