TMUX13 datasheet(29/42 Pages) TI

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Figure 11-1. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via

introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference

from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

Figure 11-2 illustrates an example of a PCB layout with the TMUX1308 and TMUX1309. Some key

considerations are:

• Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the

capacitor voltage rating is sufficient for the VDD supply.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

11.2 Layout Example

N.C.

GND

VDD

TMUX130 8

Via to G ND plane

Wide (low inductance)

trace for power

N.C.

GND

S0B

S2B

S3B

S1B

VDD

S2A

S1A

S0A

S3A

TMUX130 9

Wide (low inductance)

trace for power

Figure 11-2. TMUX1308 and TMUX1309 Layout Example

www.ti.com

TMUX1308, TMUX1309

SCDS426C – MARCH 2020 – REVISED AUGUST 2020

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Product Folder Links: TMUX1308 TMUX1309

TMUX13 Datasheet(PDF) 29 Page - Texas Instruments

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