Data Sheet

ADRF5026

Rev. A | Page 9 of 13

THEORY OF OPERATION

The ADRF5026 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

filter high frequency noise.

All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V,

and no dc blocking capacitors are required at the RF ports

when the RF potential is equal to 0 V.

The RF ports are internally matched to 50 Ω. Therefore,

external matching networks are not required. Impedance

matching on the RF transmission lines can improve insertion

loss and return loss performance at high frequencies.

The ADRF5026 integrates a driver to perform logic function

internally and to provide the advantage of a simplified control

interface. The driver features two digital control input pins,

CTRL and EN. When the EN pin is logic low, the logic level

applied to the CTRL pin determines which RF port is in

insertion loss state and which RF port is in isolation state.

The ADRF5026 supports an all off state control. When the EN

pin is logic high, both the RF1 to RFC path and the RF2 to RFC

path are in an isolation state, regardless of the logic state of the

CTRL pin. The RF1 and RF2 ports are terminated to internal

50 Ω resistors, and the RFC port becomes open reflective (see

Table 5).

The ADRF5026 design is bidirectional with equal power

to the RFC port or the RF1 or RF2 port. The isolation path

provides high loss between the unselected RFx port and the

insertion loss path.

The ideal power-up sequence is as follows:

1.

Connect GND.

2.

Power up VDD and VSS. Power up VSS after VDD to

avoid current transients on VDD during ramp-up.

3.

Apply the digital control inputs. The relative order of the

digital control inputs is not important. However, powering

the digital control inputs before the VDD supply may

inadvertantly forward bias and damage the internal ESD

protection structures. To avoid this damage, use a series

1 kΩ resistor to limit the current flowing in to the control

pin. Use pull-up or pull-down resistors if the controller

output is in a high impedance state after VDD is powered

up and the control pins are not driven to a valid logic state.

4.

Apply an RF input signal to RFC, RF1, or RF2.

The ideal power-down sequence is the reverse order of the

power-up sequence.

Table 5. Control Voltage Truth Table

Digital Control Input

RF Paths

EN

CTRL

RF1 to RFC

RF2 to RFC

Low

Low

Isolation (off)

Insertion loss (on)

Low

High

Insertion loss (on)

Isolation (off)

High

Low

Isolation (off)

Isolation (off)

High

High

Isolation (off)

Isolation (off)