MPT612 datasheet(12/37 Pages) NXP

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NXP Semiconductors

MPT612

Maximum power point tracking IC

• Separate control of output set and clear

• All I/O default to inputs after reset

7.8 10-bit ADC

The MPT612 contains one Analog-to-Digital Converter (ADC). It is a single 10-bit

successive approximation ADC with eight channels, three of which are used internally.

The ADC provides the following features:

• Measurement range from 0 V to 3.3 V

• The converter can perform more than 400 000 10-bit samples per second

• Burst conversion mode for single or multiple inputs

• Optional conversion on input pin transition or Timer Match signal

• Every analog input has a dedicated result register to reduce interrupt overhead

7.9 UARTs

The MPT612 contain two UARTs. In addition to standard transmit and receive data lines

UART1 also provides a full modem control handshake interface. The UARTs in MPT612

include a fractional baud rate generator for both UARTs. Standard baud rates such as

115200 can be achieved with any crystal frequency above 2 MHz. The UARTs provide

the following features:

• 16-byte receive and transmit FIFOs

• Register locations conform to 16C550 industry standard

• Receiver FIFO trigger points at 1-byte, 4-byte, 8-byte and 14-byte

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals

• Transmission FIFO control enables implementation of software flow control

(XON/XOFF) on both UARTs

• UART1 is equipped with standard modem interface signals. This module also

provides full support for hardware flow control (auto-CTS/RTS)

7.10 I

2C-bus serial I/O controllers

The MPT612 contains two I

2C-bus controllers.

The I

2C-bus is bidirectional, 2-wire interface providing the Serial Clock Line (SCL) and

the Serial DAta line (SDA). Each I

2C-bus device is recognized by a unique address and

can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the

capability to both receive and send information such as serial memory. Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I

2C-bus is a multi-master

bus; it can be controlled by more than one bus master connected to it.

The I

2C-bus implemented in the MPT612 supports bit rates up to 400 kbit/s (Fast

2C-bus). The controller provides the following features:

• Compliant with standard I2C-bus interface specification

• Easy to configure as master, slave or master/slave

• Programmable clocks allow versatile rate control

• Bidirectional data transfer between masters and slaves

MPT612

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Product data sheet

Rev. 2 — 14 September 2010

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