ADSP-21486KSWZ-2AB datasheet(17/71 Pages) AD

17 / 71 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. H

Page 17 of 71

February 2020

CLK_CFG1–0

Core to CLKIN Ratio Control. These pins set the start up clock frequency.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset. The

allowed values are:

00 = 8:1

01 = 32:1

10 = 16:1

11 = reserved

CLKIN

Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures

the processors to use either its internal clock generator or an external clock source.

Connecting the necessary components to CLKIN and XTAL enables the internal clock

generator. Connecting the external clock to CLKIN while leaving XTAL unconnected

configures the processors to use the external clock source such as an external clock

oscillator. CLKIN may not be halted, changed, or operated below the specified

frequency.

XTAL

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

RESET

Processor Reset. Resets the processor to a known state. Upon deassertion, there is a

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

RESETOUT/

RUNRSTIN

I/O (ipu)

Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also

has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL

BOOT_CFG2–0

Boot Configuration Select. These pins select the boot mode for the processor (see

Table 9). The BOOT_CFG pins must be valid before RESET (hardware and software) is

asserted.

1 The MLB pins are only available on the automotive models.

Table 12. Pin List, Power, Ground and Other

Name

Type

Description

VDD_INT

Internal Power Supply

VDD_EXT

I/O Power Supply

GND1

Ground

VDD_THD

Thermal Diode Power Supply. When not used, this pin can be left floating.

DNC

Do Not Connect. Do not make any electrical connection to this pin.

1 The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the

exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided

in the package.

Table 11. Pin Descriptions (Continued)

Name

Type

State

During/

After Reset

Description

The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

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