ADSP-21486KSWZ-2AB datasheet(19/71 Pages) AD

19 / 71 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. H

Page 19 of 71

February 2020

ELECTRICAL CHARACTERISTICS

266 MHz / 300 MHz / 350 MHz / 400 MHz / 450 MHz

Parameter1

Description

Conditions

Min

Typ

Max

Unit

VOH

High Level Output

Voltage

@ VDD_EXT = Min,

IOH = –1.0 mA

2.4

VOL

Low Level Output

Voltage

@ VDD_EXT = Min,

IOL = 1.0 mA

0.4

IIH

4, 5

High Level Input Current @ VDD_EXT = Max,

VIN = VDD_EXT Max

μA

IIL

Low Level Input Current @ VDD_EXT = Max, VIN = 0 V

μA

IILPU

Low Level Input Current

Pull-up

@ VDD_EXT = Max, VIN = 0 V

200

μA

IOZH

6, 7

Three-State Leakage

Current

@ VDD_EXT = Max,

VIN = VDD_EXT Max

μA

IOZL

Three-State Leakage

Current

@ VDD_EXT = Max, VIN = 0 V

μA

IOZLPU

Three-State Leakage

Current Pull-up

@ VDD_EXT = Max, VIN = 0 V

200

μA

IOZHPD

Three-State Leakage

Current Pull-down

@ VDD_EXT = Max,

VIN = VDD_EXT Max

200

μA

IDD_INT

Supply Current (Internal) fCCLK > 0 MHz

Table 14 + Table 15

× ASF

IDD_INT

Supply Current (Internal) VDDINT = 1.1 V, ASF = 1,

TJ = 25°C

385 / 410 / 450 / 500 / 550

CIN

10, 11

Input Capacitance

TJ = 25°C

1 Specifications subject to change without notice.

2 Applies to output and bidirectional pins: ADDR23–0, DATA15–0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT MLBSIG, MLBDAT, MLBDO,

MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.

3 See Output Drive Currents on Page 55 for typical drive current capabilities.

4 Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

5 Applies to input pins with internal pull-ups: TRST, TMS, TDI.

6 Applies to three-statable pin: TDO.

7 Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

8 Applies to three-statable pin with pull-down: SDCLK.

9 See Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC Processors (EE-348) for further information.

10Applies to all signal pins.

11Guaranteed, but not tested.

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