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DRA821 Datasheet(PDF) 3 Page - Texas Instruments |
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DRA821 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 228 page  4 Functional Block Diagram Figure 4-1 is functional block diagram for the device. Navigator Subsystem Interconnect High-Speed Serial Interfaces Audio Peripherals 3x MCASP 10/100/1000 Ethernet (A) DRA821 1x PCIe 4-Lane Port (B) ® intro_001 512KB L2 with ECC 1MB Shared L2 Cache with ECC Dual Arm ® ® Cortex -A72 System Services Spinlock GP Timers Mailboxes Debug UDMA WWDT Navigator Subsystem Channelized FW MCRC RA INTR UDMA INTA Proxy DMSC Safety DTK SP RAM 512B 10x GP Timers 2x RTI/WWDT SA2UL MCU Island 1 MB SRAM Channelized FW CPTS Mailbox TIMER-MGR PVU INTR SecProxy MCRC INTA UDMA Proxy/RA Spinlock Securiry Accelerators RNG DES AES SHA PKA 3DES Media and Data Storage 1x eMMC 1x SD/SDIO 1x USB 3.0 DRD (B) Automotive Interfaces 2x CAN-FD (A) Ethernet Switch (Up to 4-ports QSGMII/SGMII/RGMII/RMII) (B) GPIO 2x Arm ® Cortex -R5F ® (with optional Lockstep) 18x CAN-FD Control Interfaces 6x EPWM 3x CAP E 3x QEP E Memory Subsystem MSMC 1MB SRAM with ECC EMIF 1x32 LPDDR4 w ECC ith 512KB SRAM ELM GPMC 2x Arm ® Cortex -R5F ® (with optional Lockstep) 64K L2 RAM per Core General Connectivity 4x GPIO 3x MCSPI 7x I2C 3x I2C (A) (A) 1x OSPI or 1x HyperBus (A)(C) 1x I3C (A) 1x I3C 8x MCSPI 2x UART (A) 10x UART 1x ADC (A) (D) (D) 2x WKUP GPIO A. Both WKUP and MCU domain instances are located on the MCU island but available for the full system to access. B. SGMII, USB3.0, and PCIE share total of four SerDes lanes. A maximum of two of the three IP (for example, SGMII and USB) can be used concurrently. C. Flash interface can be configured as OSPI0, or HyperBus. D. One port is internally connected only. Not connected to any pins. Figure 4-1. Functional Block Diagram www.ti.com DRA821U, DRA821A SPRSP57A – APRIL 2020 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DRA821U DRA821A |
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