11 Layout

11.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example

(BEST) maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

1W min.

W

Figure 11-1. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via

introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference

from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

Figure 11-2 illustrates an example of a PCB layout with the TMUX7219. Some key considerations are:

• Decouple the supply pins with a 0.1-µF and 1 µF capacitor, placed lowest value capacitor as close to the pin

as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground

planes.

11.2 Layout Example

D

S1

GND

SEL

VDD

TMUX721 9

EN

Wide (low inductance)

trace for power

S2

C

Via to g round pla ne

Wide (low inductance)

trace for power

C

Figure 11-2. TMUX7219 Layout Example

TMUX7219

SCDS407A – JANUARY 2019 – REVISED NOVEMBER 2020

www.ti.com

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