MAX5548 datasheet(3/15 Pages) MAXIM

3 / 15 page

Dual, 8-Bit, Programmable, 30mA

High-Output-Current DAC

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ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k

Ω; compliance voltage = (VDD - 0.6V),

VSCLK/SCL = 0, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DAC-to-DAC Current Matching

VDD = +3V, RL = 65

Ω, CL = 24pF

400

Wake-Up Time

VDD = +5V, no load

µs

POWER SUPPLIES

Supply Voltage

VDD

+2.70

+5.25

Supply Current

IDD

VDD = +5.25V, no load

Shutdown Current

1.2

µA

LOGIC AND CONTROL INPUTS

+2.7V

≤ VDD ≤ +3.4V

0.7 x

VDD

Input High Voltage (Note 5)

VIH

+34V < VDD

≤ +5.25V

2.4

Input Low Voltage

VIL

(Note 5)

0.8

Input Hysteresis

VHYS

0.1 x

VDD

Input Capacitance

CIN

Input Leakage Current

IIN

±1

µA

Output Low Voltage

VOL

ISINK = 3mA

0.6

Output High Voltage

VOH

ISOURCE = 2mA

VDD -

0.5

I2C TIMING CHARACTERISTICS (Figure 2)

SCL Clock Frequency

fSCL

400

kHz

Setup Time for START Condition

tSU:STA

600

Hold Time for START Condition

tHD:STA

600

SCL Pulse-Width Low

tLOW

130

SCL Pulse-Width High

tHIGH

600

Data Setup Time

tSU:DAT

100

Data Hold Time

tHD:DAT

070

SCL Rise Time

tRCL

20 + 0.1

x CB

300

SCL Fall Time

tFCL

20 + 0.1

x CB

300

SDA Rise Time

tRDA

20 + 0.1

x CB

300

SDA Fall Time

tFDA

20 + 0.1

x CB

300

Bus Free Time Between a STOP

and START Condition

tBUF

1.3

µs

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