Dual, 8-Bit, Programmable, 30mA

High-Output-Current DAC

4

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ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Setup Time for STOP Condition

160

ns

Maximum Capacitive Load for

Each Bus Line

400

pF

SPI TIMING CHARACTERISTICS (Figure 6)

SCLK Clock Period

100

ns

SCLK Pulse-Width High

40

ns

SCLK Pulse-Width Low

40

ns

CS Fall to SCLK Rise Setup Time

25

ns

SCLK Rise to CS Rise Hold Time

50

ns

DIN Setup Time

40

ns

DIN Hold Time

0ns

SCLK Fall to DOUT Transition

40

ns

CS Fall to DOUT Enable

40

ns

CS Rise to DOUT Disable

40

ns

SCLK Rise to CS Fall Delay

50

ns

CS Rise to SCLK Rise Hold Time

40

ns

CS Pulse-Width High

100

ns

SPI TIMING CHARACTERISTICS FOR DAISY CHAINING (Figure 6)

SCLK Clock Period

200

ns

SCLK Pulse-Width High

80

ns

SCLK Pulse-Width Low

80

ns

CS Fall to SCLK Rise Setup Time

25

ns

SCLK Rise to CS Rise Hold Time

50

ns

DIN Setup Time

40

ns

DIN Hold Time

0ns

SCLK Fall to DOUT Transition

40

ns

CS Fall to DOUT Enable

40

ns

CS Rise to DOUT Disable

40

ns

SCLK Rise to CS Fall Delay

50

ns

CS Rise to SCLK Rise Hold Time

40

ns

CS Pulse-Width High

100

ns

Note 2: INL linearity is guaranteed from code 15 to code 255.

Note 3: Connect a resistor from FSADJ_ to GND to adjust the full-scale current. See the Reference Architecture and Operation section.

Note 4: Settling time is measured from (0.25 x full scale) to (0.75 x full scale).

0.5V). See the Supply Current vs. Digital Input Voltage graph in the Typical Operating Characteristics.