V386

V386 Datasheet

7

5/25/05

Revision 2.0

Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

Timing Diagrams

Figure 1a. “Worst Case” Test Pattern

Figure 1b. 16-Grayscale Test-Pattern Waveforms

Figure 2. V386 CMOS/TTL Output Load and Transition Time

CLKIN/CLKOUT

T

ODD Data In/Data Out

EVEN Data In/Data Out

CLKOUT

D0, 8, 16

D1, 9, 17

D2, 10, 18

D3, 11, 19

D4-7, 12-15, 20-23

D24-27

V386 CMO/TTL Output Load and Transition Times

20%

20%

80%

80%

CLHT

CHLT

CMOS/TTL Output

8pF