V386

V386 Datasheet

8

5/25/05

Revision 2.0

Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

Figure 3. V386 SETUP/HOLD and High/Low Times

Figure 4. V386 Clock In to Clock Out Delay

Figure 5. V386 Phase Lock Loop Set Time

Figure 6. V386 Power Down Delay

CLKOUT

D0 – D27 Out

0.8 V

2.0 V

RCOP

2.0 V

2.0 V

0.8 V

RCOH

RCOL

RSRC

RHRC

2.0 V

SETUP

2.0 V

HOLD

CLKOUT

Vdiff=0V

RCCD

RCK

1.5V

CLKOUT

RPLLS

RCK

3.0 V

2.0 V

3.6 V

VCC

PWRDWN

RPDD

1.5 V

PWRDWN

RCK IN

Low