V386

V386 Datasheet

1

5/25/05

Revision 2.0

Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

General Description

The V386 is an ideal LVDS receiver that converts 4-pair

LVDS data streams into parallel 28 bits of CMOS/TTL

data with bandwidth up to 2.38 Gbps throughput or

297.5 Mbytes per second.

This chip is an ideal means to solve EMI and cable size

problems associated with wide, high-speed TTL

interfaces through very low-swing LVDS signals.

ICS manufactures a large variety of video application

devices. Consult ICS for all of your video application

requirements.

Pin Assignments

Features

DS90CF386, THine THC63LVDF84, TI

SN65LVDS94

bits of CMOS/TTL data

Block Diagram

12

1

11

2

10

RxOUT22

3

9

RxOUT23

4

5

6

7

8

16

15

14

13

56-pin TSSOP

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

RxOUT24

GND

RxOUT26

RxOUT27

RxOUT25

RxIN0-

RxIN0+

RxIN1-

RxIN1+

LVDS_VCC

LVDS_GND

RxIN2-

RxIN2+

RxCLKIN-

RxCLKIN+

LVDS_GND

PLL_GND

PLL_VCC

PLL_GND

RxOUT2

RxOUT1

VCC

RxOUT8

RxOUT12

VCC

RxOUT3

RxOUT4

RxOUT5

GND

RxOUT6

RxOUT7

RxOUT9

GND

RxOUT10

RxOUT11

VCC

RxOUT13

GND

RxOUT14

RxOUT15

RxOUT16

VCC

V386

PWRDWN

RxCLKOUT

RxOUT0

49

50

51

52

53

54

55

56

LVDS_GND

RxIN3-

RxIN3+

GND

RxOUT17

RxOUT18

RxOUT19

RxOUT20

RxOUT21

RxIN0-

RxIN0+

RxIN1-

RxIN1+

RxIN2-

RxIN2+

RxCLKIN-

RxCLKIN+

RxIN3-

RxIN3+

LVDS to TTL

De-serializer

RED

PLL

GREEN

BLUE

VSYNC

RxCLKOUT

PWRDWN

HSYNC

DATA ENABLE

CONTROL

8

8

8

V386