RA6M2 datasheet(64/100 Pages) RENESAS

64 / 100 page

R01DS0357EJ0100 Rev.1.00

Page 64 of 100

Oct 8, 2019

RA6M2 Group

2. Electrical Characteristics

Figure 2.54

SPI timing for slave when CPHA = 1

2.3.12

QSPI Timing

Note 1.

tPcyc: PCLKA cycle.

Note 2.

N is set to 0 or 1 in SFMSLD.

Note 3.

N is set to 0 or 1 in SFMSHD.

Figure 2.55

QSPI clock timing

Table 2.26

QSPI timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit*1

Test conditions

QSPI

QSPCK clock cycle

tQScyc

248

tPcyc

Figure 2.55

QSPCK clock high pulse width

tQSWH

tQScyc × 0.4

QSPCK clock low pulse width

tQSWL

tQScyc × 0.4

Data input setup time

tSu

Figure 2.56

Data input hold time

tIH

QSSL setup time

tLEAD

(N+0.5) x

tQscyc - 5 *2

(N+0.5) x

tQscyc +100 *2

QSSL hold time

tLAG

(N+0.5) x

tQscyc - 5 *3

(N+0.5) x

tQscyc +100 *3

Data output delay

tOD

-4

Data output hold time

tOH

-3.3

Successive transmission delay

tTD

116

tQScyc

SSLAn

input

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

MISOn

output

MOSIn

input

tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

SPI

n = A or B

tQScyc

QSPCLK output

tQSWH

tQSWL

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