RA6M2 datasheet(13/100 Pages) RENESAS

13 / 100 page

R01DS0357EJ0100 Rev.1.00

Page 13 of 100

Oct 8, 2019

RA6M2 Group

1. Overview

SDRAM interface

CKE

Output

SDRAM clock enable signal

SDCS

Output

SDRAM chip select signal, active-low

RAS

Output

SDRAM low address strobe signal, active-low

CAS

Output

SDRAM column address strobe signal, active-low

Output

SDRAM write enable signal, active-low

DQM0

Output

SDRAM I/O data mask enable signal for DQ07 to DQ00

DQM1

Output

SDRAM I/O data mask enable signal for DQ15 to DQ08

A00 to A15

Output

Address bus

DQ00 to DQ15

I/O

Data bus

GPT

GTETRGA,

GTETRGB,

GTETRGC,

GTETRGD

Input

External trigger input pins

GTIOC0A to

GTIOC13A,

GTIOC0B to

GTIOC13B

I/O

Input capture, output compare, or PWM output pins

GTIU

Input

Hall sensor input pin U

GTIV

Input

Hall sensor input pin V

GTIW

Input

Hall sensor input pin W

GTOUUP

Output

3-phase PWM output for BLDC motor control (positive U phase)

GTOULO

Output

3-phase PWM output for BLDC motor control (negative U phase)

GTOVUP

Output

3-phase PWM output for BLDC motor control (positive V phase)

GTOVLO

Output

3-phase PWM output for BLDC motor control (negative V phase)

GTOWUP

Output

3-phase PWM output for BLDC motor control (positive W phase)

GTOWLO

Output

3-phase PWM output for BLDC motor control (negative W phase)

AGT

AGTEE0, AGTEE1

Input

External event input enable signals

AGTIO0, AGTIO1

I/O

External event input and pulse output pins

AGTO0, AGTO1

Output

Pulse output pins

AGTOA0, AGTOA1

Output

Output compare match A output pins

AGTOB0, AGTOB1

Output

Output compare match B output pins

RTC

RTCOUT

Output

Output pin for 1-Hz or 64-Hz clock

RTCIC0 to RTCIC2

Input

Time capture event input pins

SCI

SCK0 to SCK9

I/O

Input/output pins for the clock (clock synchronous mode)

RXD0 to RXD9

Input

Input pins for received data (asynchronous mode/clock synchronous mode)

TXD0 to TXD9

Output

Output pins for transmitted data (asynchronous mode/clock synchronous

mode)

CTS0_RTS0 to

CTS9_RTS9

I/O

Input/output pins for controlling the start of transmission and reception

(asynchronous mode/clock synchronous mode), active-low

SCL0 to SCL9

I/O

Input/output pins for the IIC clock (simple IIC mode)

SDA0 to SDA9

I/O

Input/output pins for the IIC data (simple IIC mode)

SCK0 to SCK9

I/O

Input/output pins for the clock (simple SPI mode)

MISO0 to MISO9

I/O

Input/output pins for slave transmission of data (simple SPI mode)

MOSI0 to MOSI9

I/O

Input/output pins for master transmission of data (simple SPI mode)

SS0 to SS9

Input

Chip-select input pins (simple SPI mode), active-low

IIC

SCL0 to SCL2

I/O

Input/output pins for the clock

SDA0 to SDA2

I/O

Input/output pins for data

SSIE

SSIBCK0

I/O

SSIE serial bit clock pins

SSILRCK0/SSIFS0

I/O

LR clock/frame synchronization pins

SSITXD0

Output

Serial data output pins

SSIRXD0

Input

Serial data input pins

SSIDATA0

I/O

Serial data input/output pins

AUDIO_CLK

Input

External clock pin for audio (input oversampling clock)

Table 1.16

Pin functions (2 of 5)

Function

Signal

I/O

Description

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