TMP139AIYAHR datasheet(26/58 Pages) TI

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0x81

0x00

Sr or P

S or Sr

DISINT

ACK/NACK

R/W=0

PEC

HID2

HID1

HID0

ACK/NACK

R/W=0

Figure 7-32. DISEC CCC Direct with PEC Enabled

Note

TMP139 NACKs the DISEC CCC if the previous transaction has a parity or PEC error and the host

starts the transaction with a Repeated Start.

7.4.6.3 RSTDAA CCC

When the RSTDAA CCC is issued by the host controller to the TMP139, it shall switch from I3C basic mode to

I2C mode. The CCC takes effect after a Stop has been issued by the host controller. Once the RSTDAA is

received, the TMP139 shall perform the following actions:

• Update the MR18 register bit INF_SEL as 1'b0 for I2C mode of operation.

• Update the MR18 register bit PEC_EN as 1'b0 to disable PEC, if it was previously enabled.

• Update the MR18 register bit PAR_DIS as 1'b0 to enable parity check, if it was previously disabled.

• Update the MR27 register bit IBI_ERROR_EN as 1'b0 to disable IBI, if it was previously enabled.

The command is always issues as a broadcast command as shown in Figure 7-33.

0x06

Sr or P

S or Sr

ACK/NACK

R/W=0

Figure 7-33. RSTDAA CCC Broadcast

The command may also be issued with PEC enabled, as shown in Figure 7-34. In such a case, the host

controller shall append the PEC byte calculated on all bytes except the byte with 7'h7E and R/W=0 after the

Start or Repeated Start.

0x06

Sr or P

S or Sr

ACK/NACK

R/W=0

PEC

Figure 7-34. RSTDAA CCC Broadcast with PEC

Note

TMP139 NACKs the RSTDAA CCC if the previous transaction has a parity or PEC error and the host

starts the transaction with a Repeated Start.

7.4.6.4 SETAASA CCC

When the SETAASA CCC is issued by the host controller to the TMP139, it shall switch from I2C mode to I3C

basic mode. The CCC takes effect after a Stop has been issued by the host controller. Once the SETAASA is

received, the TMP139 shall set the MR18 register bit INF_SEL as 1'b1 for I3C basic mode of operation.

The CCC is always issues as a broadcast command, as shown in Figure 7-35, with no PEC bytes since it is

applicable only during I2C mode.

TMP139

SNIS217 – DECEMBER 2020

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