TMP139AIYAHR datasheet(20/58 Pages) TI

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7.4.4.4 Host I3C Read Operation with PEC

As shown in Figure 7-17 and Figure 7-18, when the PEC is enabled by the host, an additional byte is added by

the host after sending the register address. The format for the additional byte is described in Table 7-5. Since

only one and two byte reads are permitted by the CMD byte, the device shall terminate the read phase after

sending one byte of data and PEC byte or two byte of data and PEC byte, followed by the T-bit as 0. In an

unlikely case where the host sets the register address as 255, and attempts a read of two bytes, the device

result is not guaranteed.

S or Sr

HID2

HID1

HID0

R/W=0

RA = Register Address [7:0]

ACK/NACK

Data(RA)

...

Data(RA+N)

T=1

PEC

Sr or P

T=0

HID2

HID1

HID0

R/W=1

ACK/NACK

CMD

R=1

PEC

Figure 7-17. I3C Basic Mode Read with PEC enabled

HID2

HID1

HID0

R/W=0

RA = Register Address [7:0]

ACK/NACK

Data(RA)

...

Data(RA+N)

T=1

PEC

Sr or P

T=0

HID2

HID1

HID0

R/W=1

ACK/NACK

R/W=0

ACK

CMD

R=1

PEC

Figure 7-18. I3C Basic Mode Read with PEC enabled and IBI Header

If the CMD value sent by the host is not valid for TMP139, the device shall NACK the read phase.

The TMP139 shall NACK the read phase of the transaction if there was a parity error in the write phase before

the Repeated Start. If the host attempts to start a new transaction with a Repeated Start to the same device,

then TMP139 shall NACK the device address to indicate an error condition to the host. The host must first clear

the parity error condition before performing any new transfer to the TMP139.

If there is a PEC error, then the TMP139 shall NACK the read phase of the transaction. If the host attempts to

start a new transaction with a Repeated Start to the same device, then TMP139 shall NACK the device address

to indicate an existing error condition to the host. The host must first clear the PEC error condition before

performing any new transfer to the TMP139.

TMP139

SNIS217 – DECEMBER 2020

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