TMP139AIYAHR datasheet(17/58 Pages) TI

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7.4.4 I3C Basic Mode Operation

As described in the previous section, I3C basic mode of operation is always entered from the I2C mode of

operation. When in the I3C basic mode, the device can support data transfer rates of up to 12.5 MHz with a

push-pull SDA driver. Additionally, the following may be supported by default or when enabled:

1. IBI: Disabled by default, the IBI can now be enabled.

2. Packet error check: Disabled by default, but the TMP139 can support the PEC feature when enabled by the

host.

3. Parity check: Is always enabled by default.

In I3C basic mode of operation, the read and write packets may have different structures. The structure of the

data payload shall be dependent on the feature that has been enabled.

7.4.4.1 Host I3C Write Operation without PEC

As shown in Figure 7-11 and Figure 7-12, an I3C basic write operation is the same as an I2C write operation. For

all bytes after the device address field, the 9th bit is the parity bit sent by the host. When the IBI is enabled by the

host, it must send the IBI header byte which consists of 7'h7E+R/W=0, before it sends the device address. This

allows the participating devices on the bus to arbitrate between themselves if more than one device has an

interrupt condition that needs to be communicated to the host.

S or Sr

HID2

HID1

HID0

R/W=0

RA = Register Address [7:0]

ACK/NACK

Data(RA)

Data(RA+1)

...

Data(RA+N)

Sr or P

Figure 7-11. I3C Basic Mode Write

HID2

HID1

HID0

R/W=0

RA = Register Address [7:0]

ACK/NACK

Data(RA)

Dat a(RA+1)

...

Dat a(RA+N)

Sr or P

R/W=0

ACK

Figure 7-12. I3C Basic Mode Write with IBI Header

If there is a parity error during the data transfer, the device shall discard all the bytes including the byte for which

parity error was detected and set the parity error condition. If the host attempts to start a new transaction with a

Repeated Start to the same device, then TMP139 shall NACK the device address to indicate an error condition

to the host. The host must first clear the parity error condition before performing any new transfer to the

TMP139. When IBI is enabled, the device can communicate to the host the error conditions seen, using IBI.

However when IBI is not enabled, it is strongly recommended that the host check the error status register to

ensure that no parity error was detected on the bus.

7.4.4.2 Host I3C Write Operation with PEC

As shown in Figure 7-13 and Figure 7-14, when the PEC is enabled by the host, an additional byte is added by

the host after sending the register address. The format for the additional byte is described in Table 7-5.

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TMP139

SNIS217 – DECEMBER 2020

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