TMS320F28062F datasheet(73/181 Pages) TI

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External Clock Signal

(Toggling 0−VDDIO)

XCLKIN/GPIO19/38

TMS320F28069, TMS320F28069F, TMS320F28069M, TMS320F28068F, TMS320F28068M

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064

TMS320F28063, TMS320F28062, TMS320F28062F

www.ti.com

SPRS698H – NOVEMBER 2010 – REVISED MARCH 2020

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TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062

TMS320F28062F

Detailed Description

(1)

The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog

reset only. A reset issued by the debugger or the missing clock detect logic has no effect.

(2)

This register is EALLOW protected. See the Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual

for more information.

(3)

By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the

PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.

Figure 6-13. Using a 3.3-V External Oscillator

6.6.3

PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking

signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control

PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing

to the PLLCR register. The watchdog module can be re-enabled (if need be) after the PLL module has

stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that

the output frequency of the PLL (VCOCLK) is at least 50 MHz.

Table 6-13. PLL Settings

PLLCR[DIV] VALUE(1) (2)

SYSCLKOUT (CLKIN)

PLLSTS[DIVSEL] = 0 or 1(3)

PLLSTS[DIVSEL] = 2

PLLSTS[DIVSEL] = 3

00000 (PLL bypass)

OSCCLK/4 (Default)(1)

OSCCLK/2

OSCCLK

00001

(OSCCLK * 1)/4

(OSCCLK * 1)/2

(OSCCLK * 1)/1

00010

(OSCCLK * 2)/4

(OSCCLK * 2)/2

(OSCCLK * 2)/1

00011

(OSCCLK * 3)/4

(OSCCLK * 3)/2

(OSCCLK * 3)/1

00100

(OSCCLK * 4)/4

(OSCCLK * 4)/2

(OSCCLK * 4)/1

00101

(OSCCLK * 5)/4

(OSCCLK * 5)/2

(OSCCLK * 5)/1

00110

(OSCCLK * 6)/4

(OSCCLK * 6)/2

(OSCCLK * 6)/1

00111

(OSCCLK * 7)/4

(OSCCLK * 7)/2

(OSCCLK * 7)/1

01000

(OSCCLK * 8)/4

(OSCCLK * 8)/2

(OSCCLK * 8)/1

01001

(OSCCLK * 9)/4

(OSCCLK * 9)/2

(OSCCLK * 9)/1

01010

(OSCCLK * 10)/4

(OSCCLK * 10)/2

(OSCCLK * 10)/1

01011

(OSCCLK * 11)/4

(OSCCLK * 11)/2

(OSCCLK * 11)/1

01100

(OSCCLK * 12)/4

(OSCCLK * 12)/2

(OSCCLK * 12)/1

01101

(OSCCLK * 13)/4

(OSCCLK * 13)/2

(OSCCLK * 13)/1

01110

(OSCCLK * 14)/4

(OSCCLK * 14)/2

(OSCCLK * 14)/1

01111

(OSCCLK * 15)/4

(OSCCLK * 15)/2

(OSCCLK * 15)/1

10000

(OSCCLK * 16)/4

(OSCCLK * 16)/2

(OSCCLK * 16)/1

10001

(OSCCLK * 17)/4

(OSCCLK * 17)/2

(OSCCLK * 17)/1

10010

(OSCCLK * 18)/4

(OSCCLK * 18)/2

(OSCCLK * 18)/1

Table 6-14. CLKIN Divide Options

PLLSTS [DIVSEL]

CLKIN DIVIDE

TMS320F28062F Datasheet(PDF) 73 Page - Texas Instruments

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