TMS320F28062F datasheet(98/181 Pages) TI

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To COMPy A or B input

To ADC Channel X

AIOx Pin

AIOxIN

AIOxINE

SYNC

SYSCLK

Logic implemented in GPIO MUX block

AIODAT Reg

(Read)

AIODAT Reg

(Latch)

AIOSET,

AIOCLEAR,

AIOTOGGLE

Regs

AIOMUX 1 Reg

(0 = Input, 1 = Output)

AIODIR Reg

(Latch)

TMS320F28069, TMS320F28069F, TMS320F28069M, TMS320F28068F, TMS320F28068M

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064

TMS320F28063, TMS320F28062, TMS320F28062F

SPRS698H – NOVEMBER 2010 – REVISED MARCH 2020

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TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062

TMS320F28062F

Detailed Description

6.9.2.2

ADC MUX

Figure 6-29. AIOx Pin Multiplexing

The ADC channel and Comparator functions are always available. The digital I/O function is available only

when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects

the actual pin state.

The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode,

reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer

is disabled to prevent analog signals from generating noise.

On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO

function disabled for that pin.

TMS320F28062F Datasheet(PDF) 98 Page - Texas Instruments