F0443 datasheet(8/65 Pages) RENESAS

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F0443 Datasheet

September 1, 2020

Pin Descriptions

Table 1.

Pin Descriptions

Pin Number

Name

Description

RFIN_A

Channel A RF input internally matched to 50Ω. Must use external DC block.

2, 11, 13,

15, 20, 22,

25, 27, 30,

34, 36, 39,

41, 46, 48

GND

Internally grounded. This pin must be grounded with a via as close to the pin as possible.

SPI_I3C_SEL

Logic control to select between SPI or I3C mode. Logic HIGH = I3C slave mode using a ‘Slave-Lite’

version of the MIPI I3C communication protocol. Logic LOW/Open = SPI slave mode. An internal pull-

down resistor of 100kΩ connects between this pin and GND.

STBY_A

Standby control for Channel A. HIGH/Open = device power OFF with SPI/I3C still powered ON, LOW =

device power ON. An internal pull-up resistor network connects between this pin and 1.67V.

CSb

Chip Select bar input. Used only for SPI mode. Logic LOW allows data to be shifted in. Logic HIGH

updates the programming register.

DATA/SDA

SPI slave data in or I3C data in/out.

CLK/SCL

SPI/I3C clock input.

ID_0

Bit 0 for the I3C static address or used for adding static addressing capability in SPI mode. See the

Programming section for details. An internal pull-down resistor of 100kΩ connects between this pin and

GND.

ID_1

Bit 1 for the I3C static address or used for adding static addressing capability in SPI mode. See the

Programming section for details. An internal pull-down resistor of 100kΩ connects between this pin and

GND.

STBY_B

Standby control for Channel B. HIGH/Open = device power OFF with SPI/I3C still powered ON, LOW =

device power ON. An internal pull-up resistor network connects between this pin and 1.67V.

RFIN_B

Channel B RF input internally matched to 50Ω. Must use external DC block.

DSA1_B

Logic control for channel B DSA1. Logic HIGH/Open = 6dB attenuation, logic LOW = 0dB attenuation. An

internal pull-up resistor network connects between this pin and 1.67V.

VCC_AMP1_B

Channel B amplifier 1 DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.

RSET1_B

Connect 2.67kΩ external resistor to GND to optimize amplifier bias. Used with RDSET1_B pin 18.

RDSET1_B

Connect 9.1kΩ external resistor to GND to optimize amplifier bias. Used with RSET1_B pin 17.

RFET_B

Connect 4.7kΩ external resistor to GND to optimize amplifier gain variation over temperature.

VCC_AMP2_B

Channel B amplifier 2 DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.

DSA3_B_BIT0

Logic control bit 0 for channel B DSA3. An internal pull-up resistor network connects between this pin and

1.67V.

DSA3_B_BIT1

Logic control bit 1 for channel B DSA3. An internal pull-up resistor network connects between this pin and

1.67V.

RFOUT_B

Channel B RF output internally matched to 50Ω. Must use external DC block.

VCC_BIAS_B

Channel B bias circuitry DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.

F0443 Datasheet(PDF) 8 Page - Renesas Technology Corp

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