F2911 Datasheet

© 2017 Integrated Device Technology, Inc.

10

Rev O, September 21, 2017

Control Mode

Table 7.

Switch Control Truth Table

V1

State

RFC to RF2

LOW

Isolation

RF1 port reflective, RF2 port matched to 75Ω

HIGH

Insertion Loss

RF1 and RF2 port matched to 75Ω

Application Information

Default Start-up

The V1 control pin includes no internal pull-down resistors to logic LOW or pull-up resistors to logic HIGH.

Power Supplies

minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to

fail. Supply voltage change or transients should have a slew rate slower than 1V/20µs. In addition, all control pins should remain at 0V

(± 0.3V) while the supply voltage ramps up or while it returns to zero.

Control Pin Interface

If a clean control signal cannot be guaranteed due to overshoot, undershoot, or ringing, etc., the following circuit at the input of the control pin

is recommended.

Figure 13. Control Pin Signal Integrity Improvement Circuit

F2911

V1

2pF

5k

Ω

EP