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F1950Z Datasheet(PDF) 5 Page - Renesas Technology Corp

Part # F1950Z
Description  Spurious Free Design Attenuation Error < 0.3 dB @ 2 GHz
PDF  20 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

F1950Z Datasheet(HTML) 5 Page - Renesas Technology Corp

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Glitch-FreeTM Digital Step Attenuator
5
Rev 3 Aug 8, 2020
PARALLEL CONTROL MODE
The user has the option of running in one of two parallel modes: Direct Parallel Mode or Latched Parallel
Mode.
DIRECT PARALLEL MODE:
Direct Parallel Mode is selected when VMODE (pin 3) is < VIL and LE (pin 16) is > VIH. In this mode the
device will immediately react to any voltage changes to the parallel control pins [pins 19, 20, 21, 22, 23,
24, 1]. Use direct parallel mode for the fastest settling time.
LATCHED PARALLEL MODE:
Latched Parallel Mode is selected when VMODE (pin 3) is < VIL and LE (pin 16) is toggled from < VIL to > VIH
To utilize Latched Parallel Mode:
Set LE < VIL
Adjust pins [19, 20, 21, 22, 23, 24, 1] to the desired attenuation setting. (Note the device will not
react to these pins while LE < VIL.)
Pull LE > VIH. The device will then transition to the attenuation settings reflected by these pins.
Latched Parallel Mode implies a default state for when the device is powered up with VMODE < VIL and LE < VIL.
In this case the default setting is MAXIMUM Attenuation.
LATCHED PARALLEL MODE TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue)
LATCHED PARALLEL MODE TIMING TABLE:
Interval
Symbol
Description
Min
Spec
Max
Spec
Units
A
Serial to Parallel Mode Setup Time
100
ns
B
Parallel Data Hold Time
10
ns
C
LE minimum pulse width
10
ns
D
Parallel Data Setup Time
10
ns
D[6:0]
Data Word
Latched into
Active Register
LE
VMODE
Spec
Intervals
A
D
C
B



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