ADC3563 datasheet(49/75 Pages) TI

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Figure 8-50. Register 0x11

SE A

DLL PDN

AZ EN

R/W-0

Table 8-18. Register 0x11 Field Descriptions

Bit

Field

Type

Reset

Description

7-6

R/W

Must write 0

SE A

R/W

This bit enables single ended analog input, channel A. In this

mode the SNR reduces by 3-dB.

0: Differential input

1: Single ended input

4-3

R/W

Must write 0

DLL PDN

R/W

This register applies ONLY to the ADC3563. It powers down the

internal DLL, which is used to adjust the sampling time. This

below 40 MSPS. When DLL PDN bit is enabled the sampling

time is directly dependent on sampling clock duty cycle (with a

50/50 duty the sampling time is TS/2).

0: Sampling time is TS/ 4

1: Sampling time is TS/2 (only for sampling rates below 40

MSPS).

R/W

Must write 0

AZ EN

R/W

0/1

This bit enables the internal auto-zero circuitry. It is enabled by

default for the ADC3561/62 and disabled for the ADC3563.

0: Auto-zero disabled

1: Auto-zero enabled

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ADC3563

SBAS990 – FEBRUARY 2021

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